## Does Removing the Coupling Capacitor from a Neural Implant Put Cortical Tissue at Risk?

**Yes — and a new circuit architecture published August 12, 2026 by Dimitris Antoniadis and Timothy Constandinou quantifies exactly how fast the damage window opens: 0.81 milliseconds.** The paper, posted to arXiv (2608.10361), targets a specific and largely unaddressed failure mode in DC-coupled analogue front ends (AFEs) used in intracortical recording devices. A single gate-oxide breakdown event in a low-noise [amplifier](https://bciintel.com/glossary/amplifier) input transistor can open a direct DC current path from the supply rail into brain tissue. The authors report their detection mechanism resolves a worst-case fault current of 6.4 nA — meeting the ISO 14708-3 limit for an electrode with an 8,533 µm² contact area — across all process corners in a 65 nm design. The work forces a direct conversation about whether the field's push toward compact, capacitor-free recording front ends has outpaced the corresponding safety engineering.

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## The Core Problem: What the Coupling Capacitor Was Actually Doing

AC-coupled AFEs have dominated implantable neural recording hardware for one straightforward reason that is rarely stated plainly: the series capacitor is a passive, intrinsic safeguard. If any active component in the signal chain fails, the capacitor physically blocks DC current from reaching the electrode-tissue interface. That protection is essentially free, requiring no sensing circuitry, no firmware, and no power budget — it simply exists.

DC-coupled designs eliminate that capacitor to reduce die area and extend bandwidth down to the true DC baseline, which matters for slow cortical potentials, infraslow oscillations, and certain local field potential (LFP) biomarkers increasingly targeted by [closed-loop BCI](https://bciintel.com/glossary/closed-loop) systems. The tradeoff has been well understood in principle, but as Antoniadis and Constandinou note, the recording-side protection problem has "gone almost unexamined" in the published literature — in stark contrast to the stimulation side, where single-fault tolerance via series DC-blocking capacitors is a regulatory requirement and engineering baseline.

The asymmetry is striking. Every intracortical stimulator deployed in humans today carries a blocking capacitor on the output path because regulators and engineers long ago established that even a brief, uncontrolled DC current injection can cause irreversible electrochemical damage to cortical tissue. Recording front ends carry exactly the same physical risk through a different failure pathway, and the field has not yet developed equivalent enforcement mechanisms.

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## The Proposed Solution: Encoding Fault Signatures in Oscillator Duty Cycle

The Antoniadis-Constandinou mechanism works by monitoring the LNA continuously for the DC imbalance that a gate-oxide breakdown event would produce. Rather than using a static threshold comparator — which adds its own failure modes and offset vulnerabilities — the design encodes the detected imbalance in the duty cycle of a current-starved relaxation oscillator. The result is read out as a time-to-digital measurement, a format that is inherently robust to supply noise and amenable to digital post-processing already present in modern neural recording ASICs.

Key figures from the paper, grounded in the source:

- **Worst-case fault current resolved:** 6.4 nA
- **Detection time:** within 0.81 ms across all process corners
- **Technology node:** 65 nm CMOS
- **ISO compliance target:** ISO 14708-3 limit for an 8,533 µm² electrode contact area
- **Mechanism response:** disables the amplifier before fault current can cause irreversible tissue damage

The 65 nm process node is notable. Much of the implantable-grade analog design community has historically worked in larger nodes (180 nm, 130 nm) for better radiation tolerance and mature process characterization. Designing at 65 nm yields smaller area — exactly the motivation for DC coupling in the first place — but also increases gate-oxide stress and leakage variability, making the fault scenario the authors target more probable, not less. The mechanism therefore addresses a hazard that scales with the same technology trends driving adoption of DC-coupled designs.

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## Why This Matters for Next-Generation High-Channel-Count Arrays

The [brain-computer interface](https://bciintel.com/glossary/brain-computer-interface) industry is in an electrode-count race. Devices are scaling from tens to hundreds to thousands of recording channels, with [Neuralink Corp](https://bciintel.com/companies/neuralink) and [Precision Neuroscience](https://bciintel.com/companies/precision-neuroscience) among the companies publicly pursuing high-density intracortical arrays. Every additional channel adds area pressure on the recording ASIC. DC-coupled front ends are an attractive path to meeting that pressure — but at scale, a single-fault event anywhere across thousands of independent recording channels becomes a probabilistic near-certainty over a multi-year implant lifetime, not an edge case.

The ISO 14708-3 standard referenced in the paper is the IEC/ISO standard governing implantable neurostimulators, and its application to the recording-side fault scenario here is analytically significant. The authors are essentially arguing — through their compliance demonstration — that the same regulatory logic that mandates DC-blocking caps on stimulation outputs should be applied, in engineering form, to recording inputs. That argument has direct implications for IDE submissions and PMA applications for any next-generation device using DC-coupled AFEs.

From a regulatory standpoint, FDA reviewers evaluating intracortical recording devices under Breakthrough Device Designation will need to engage with this failure mode explicitly if DC-coupled architectures are present. The paper gives those reviewers a quantitative framework — and a specific detection latency target — that did not previously exist in the published record.

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## Skeptical Assessment

A few caveats are warranted before this mechanism enters the design checklist for clinical devices.

**First, this is a simulation and design paper from an academic group.** The 0.81 ms detection time and 6.4 nA fault resolution are reported across process corners in simulation, not measured on fabricated silicon. Tape-out results, especially in a 65 nm node that may require specialized foundry access for biomedical applications, will be the real test. Monte Carlo variation, packaging parasitics, and in-vivo electrode impedance shifts could all affect the mechanism's behavior.

**Second, the oscillator-based readout adds its own power and area footprint.** The paper does not report final area or power numbers in the available abstract, so claims of area efficiency relative to alternative protection schemes cannot yet be independently assessed.

**Third, this addresses one specific fault mode — gate-oxide breakdown of the LNA input transistor.** Real implant reliability analysis requires a full single-fault analysis (SFA) across the entire signal chain, including biasing networks, ESD structures, and any switched-capacitor elements. The authors acknowledge this by framing the work as "opening a broader discussion," which is appropriate but also signals that the full safety architecture remains to be defined.

None of these caveats diminish the significance of identifying and quantifying the problem. The field needed a published, quantitative treatment of this failure mode, and now it has one.

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## Industry and Clinical Translation Implications

For ASIC design teams at implant companies, this paper establishes a reference architecture and a compliance target — 0.81 ms detection for a 6.4 nA fault at ISO 14708-3 limits — that can anchor internal safety verification processes. Design review conversations that previously lacked a published benchmark now have one.

For clinical teams and IRBs reviewing protocols for devices with DC-coupled front ends, the paper makes the theoretical tissue-damage pathway concrete and quantified. That shifts the conversation from "this is hypothetically possible" to "here is the fault current magnitude and the ISO electrode-size relationship that determines your margin."

For [device longevity](https://bciintel.com/glossary/device-longevity) researchers, the intersection of increasing channel counts, smaller technology nodes, and cumulative gate-oxide stress over years of implantation makes this failure mode a long-term reliability concern, not just an acute safety scenario. A mechanism that detects and disables a faulted channel without requiring full device explantation could meaningfully extend safe operational lifetime.

The paper does not address endovascular or ECoG recording architectures directly, where the electrode-tissue geometry and impedance environment differ substantially from intracortical arrays. Whether analogous fault scenarios exist in those modalities — and whether the oscillator-based detection approach scales to them — is an open question.

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## Key Takeaways

- **DC-coupled AFEs eliminate the passive safety barrier** provided by the coupling capacitor; a single gate-oxide breakdown in an LNA input transistor can inject DC current directly into cortical tissue
- **The new detection mechanism** by Antoniadis and Constandinou resolves a worst-case 6.4 nA fault within 0.81 ms, meeting ISO 14708-3 limits for an 8,533 µm² electrode, in a 65 nm CMOS design
- **The recording side has lagged the stimulation side** on single-fault safety enforcement — stimulators have required DC-blocking caps for years; equivalent protection for recorders has been largely unexamined
- **High-channel-count scaling increases aggregate fault probability** over multi-year implant lifetimes; the failure mode is not theoretical at scale
- **Results are simulation-based**; fabricated silicon validation and full SFA across the signal chain are the next required steps before clinical integration
- **Regulatory relevance is immediate**: FDA reviewers of DC-coupled intracortical recording devices under IDE or PMA now have a quantitative framework for evaluating recording-side single-fault protection

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## Frequently Asked Questions

**What is a DC-coupled analogue front end in a neural implant?**
A DC-coupled AFE connects the recording electrode directly to the amplifier input without a series capacitor, allowing the circuit to capture signals down to 0 Hz (true DC). This reduces die area compared to AC-coupled designs but removes the capacitor's passive protection against DC fault currents reaching the tissue.

**Why is a single-fault event in a neural implant dangerous?**
If a component such as an LNA input transistor undergoes gate-oxide breakdown, it can create a direct low-impedance path from a voltage supply rail to the electrode tip in cortical tissue. Even small, sustained DC currents — in the nanoampere range — can cause irreversible electrochemical damage to neurons and surrounding tissue through electrolysis and pH changes.

**What does ISO 14708-3 require for implantable neural devices?**
ISO 14708-3 covers implantable neurostimulators and sets limits on the charge and current that can be delivered to tissue under fault conditions. The Antoniadis-Constandinou paper uses it as a compliance target for the recording-side fault scenario, linking the allowable fault current to the electrode contact area (8,533 µm² in their reference case).

**Does this fault risk apply to ECoG or endovascular BCI devices?**
The paper focuses on intracortical recording front ends. ECoG and endovascular devices operate with different electrode geometries, larger contact areas, and different tissue-proximity profiles, which changes both the fault current thresholds and the clinical consequences. The authors do not extend their analysis to those modalities, and that generalization remains an open research question.

**What needs to happen before this mechanism appears in a clinical device?**
Fabricated silicon measurements are the immediate next step to validate the simulated 0.81 ms detection time and 6.4 nA fault resolution. Beyond that, integration into a full recording ASIC, comprehensive single-fault analysis across the entire signal chain, in-vivo electrode impedance characterization, and biocompatibility assessment of the overall system would all be required before an IDE submission incorporating this architecture could be expected to satisfy FDA reviewers.

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*This article is based on a preprint posted to arXiv (2608.10361) and has not yet undergone peer review. The findings represent simulation results from an academic feasibility study and should not be interpreted as verified performance of a clinical device. This content is for informational purposes only and does not constitute medical or regulatory advice.*